1. Field of the Invention
The present invention relates to a level shifter that is employed in a driver circuit of an image display device (active matrix image display device) for displaying information such as an image by means of switching elements and pixels arranged in matrix.
2. Description of the Related Art
In recent years, the fining of a technique in manufacturing semiconductors is advancing. Further, because of the popularized electronic equipment such as a portable equipment which demands low consumption power, the LSI that is used in these equipments has become 3.3 V, that is, a 3.3 V low power source voltage drive has become the mainstream. On the other hand, in a liquid crystal display, which is recently in high demand for its use as a monitor of a portable terminal, computer, etc., a liquid crystal drive is conducted by a 10 to 20 V of voltage amplitude signal. Thus, it has become necessary to provide at least a circuit portion that operates at a high power source voltage corresponding to the voltage amplitude of the driver circuit thereof.
Therefore, between the low voltage amplitude signal of a controller LSI and the high voltage amplitude signal that is necessary to drive the liquid crystal display, a level shifter for performing a voltage amplitude conversion becomes indispensable.
A conventional level shifter that is generally used is shown in FIG. 23. This level shifter converts a signal having a 0 to VDD1 ( greater than 0, for example 5 V) voltage amplitude to a signal having a 0 to VDD2 ( greater than VDD1, for example 10 V) voltage amplitude. That is, it is a level shifter which shifts a high electric potential side while a low electric potential side is fixed. The structure thereof is as follows. A source of a P channel MOS transistor (hereinafter abbreviated as PMOST) 101 and a source of a PMOST 102 are each connected to a power source VDD2, and a drain of the PMOST 101 is connected to a source of a PMOST 103 while a drain of the PMOST 102 is connected to a source of a PMOST 104, respectively. Further, a drain of the PMOST 103 is connected to a gate of the PMOST 102 and to a drain of an N channel MOS transistor (hereinafter abbreviated as NMOST) 105, and drain of the PMOST 104 is connected to a gate of the PMOST 101 and to a drain of an NMOST 106. A source of the NMOST 105 and a source of the NMOST 106 are connected to a GND (0 V). Furthermore, an input signal (IN) is fed to the gate of the PMOST 103 and that of the NMOST 105 while an inverted input signal (/IN) of the input signal (IN) is fed to the gate of the PMOST 104 and that of the NMOST 106, respectively, to thereby extract an output signal (OUT) from the drain of the NMOST 106. It is to be noted that an inverted output signal (/OUT) of the above output signal can be extracted from the drain of the NMOST 105.
Note that in regards to the power source voltage, the VDD# of the power source is expressed as power source VDD# (where # denotes a number) throughout the present specification. Further, GND, VDD1, VDD2, VDD3, and VDD4 will be taken as the 5 kinds of power source voltage and their relationship according to the voltage level satisfies VDD4 less than VDD3 less than GND less than VDD1 less than VDD2. However, the voltage of GND is set to 0 V in order to simplify the explanation.
A basic operation of the example of the conventional level shifter will be explained next. When the electric potential of the input signal (IN) is xe2x80x9cHixe2x80x9d of VDD1, then the NMOST 105 is turned ON and the PMOST 103 is turned OFF, whereby the electric potential xe2x80x9cLoxe2x80x9d of GND is fed to the gate of the PMOST 102 to thereby turn the PMOST 102 ON. On the other hand, the electric potential of the inverted input signal (/IN) is xe2x80x9cLoxe2x80x9d of GND, and thus the NMOST 106 is turned OFF while the PMOST 104 is turned ON. Therefore, both PMOSTs 102 and 104 are turned ON and the electric potential is shifted, whereby the output signal (OUT) becomes xe2x80x9cHixe2x80x9d of VDD2. It is to be noted that the PMOST 101 becomes OFF to thereby ensure that the gate of the PMOST 102 is held at the xe2x80x9cLoxe2x80x9d level of GND by the electric potential.
When the electric potential of the input signal (IN) is xe2x80x9cLoxe2x80x9d of GND, the level shifter shown in FIG. 23 takes a symmetrical structure. Thus, similar to the above, it can be comprehended that the electric potential xe2x80x9cLoxe2x80x9d of GND (0 V) is outputted from the output terminal (OUT).
Accordingly, a signal having a voltage amplitude of 0 to VDD1 is thus converted to a signal having a voltage amplitude of 0 to VDD2.
Next, an example of a conventional level shifter which shifts the low electric potential side while the high electric potential side is fixed is shown in FIG. 24. This level shifter converts a signal having a VDD3 ( less than 0) to 0 voltage amplitude to a signal having a VDD4 ( less than VDD3) to 0 voltage amplitude. The structure thereof is as follows. A source of an NMOST 107 and a source of an NMOST 108 are each connected to the power source VDD4, and a drain of the NMOST 107 is connected to a source of an NMOST 109 while a drain of the NMOST 108 is connected to a source of an NMOST 110, respectively. Further, a drain of the NMOST 109 is connected to a gate of the NMOST 108 and to a drain of a PMOST 111, and drain of the NMOST 110 is connected to a gate of the NMOST 107 and to a drain of a PMOST 112. A source of the PMOST 111 and a source of the PMOST 112 are connected to the GND (0 V). Furthermore, an input signal (IN) is fed to the gate of the NMOST 109 and that of the PMOST 111 while an inverted input signal (/IN) of the input signal (IN) is fed to the gate of the NMOST 110 and that of the PMOST 112, respectively, to thereby extract an output signal (OUT) from the drain of the PMOST 112. It is to be noted that an inverted output signal (/OUT) of the above output signal (OUT) can be extracted from the drain of the PMOST 111.
A basic operation of the example of the conventional level shifter shown in FIG. 24 will be explained next. When the electric potential of the input signal (IN) is xe2x80x9cLoxe2x80x9d of VDD3, then the PMOST 111 is turned ON and the NMOST 109 is turned OFF, whereby the electric potential xe2x80x9cHixe2x80x9d of GND is fed to the gate of the NMOST 108 to thereby turn the NMOST 108 ON. On the other hand, the electric potential of the inverted input signal (/IN) is xe2x80x9cHixe2x80x9d of GND, and thus the PMOST 112 is turned OFF while the NMOST 110 is turned ON. Therefore, both NMOSTs 108 and 110 are turned ON and the electric potential is shifted, whereby the output signal (OUT) becomes xe2x80x9cLoxe2x80x9d of VDD4. It is to be noted that the NMOST 107 becomes OFF to thereby ensure that the gate of the NMOST 108 is held at the xe2x80x9cHixe2x80x9d level of GND by the electric potential.
When the electric potential of the input signal (IN) is xe2x80x9cHixe2x80x9d of GND, the level shifter shown in FIG. 24 takes a symmetrical structure. Thus, similar to the above, it can be comprehended that the electric potential xe2x80x9cHixe2x80x9d of GND is outputted from the output terminal (OUT).
Accordingly, the signal having a voltage amplitude of VDD3 to 0 is thus converted to a signal having a voltage amplitude of VDD4 to 0.
The above described example of the conventional level shifter can comparatively easily perform level conversion between voltage amplitudes having a small difference. However, as the difference between the voltage amplitudes becomes large, it becomes more difficult for the level shifter to perform level conversion, resulting in the occurrence of problems. These problems will be explained in the following.
Although the basic operation of the exemplified conventional level shifter was simply explained in the above, precisely, points such as to perform an operation or not or the operating time are determined depending on the voltage amplitude to be converted, the characteristic of the transistor, and the like. In the level shifter shown in FIG. 23, for example, let""s assume that VDD1=5 V, VDD2=15 V, a threshold voltage of the PMOST 101 to 104 is xe2x88x922 V, and a threshold voltage of the NMOST 105 and 106 is 2 V. Under these conditions and under a steady state of a normal operating time as well, if the electric potential of the input signal (IN) is changed from the xe2x80x9cLoxe2x80x9d of 0 V to the xe2x80x9cHixe2x80x9d of 5 V, then the voltage between the gate and the source of the NMOST 105 exceeds the threshold voltage thereof, thereby turning the NMOST 105 ON. On the other hand, because the source electric potential of the PMOST 103 is initially 15 V, the voltage between the gate and the source the PMOST 103 is xe2x88x9210 V, which exceeds the threshold voltage thereof, and the PMOST 103 is also turned ON. The PMOST 101 is also in the ON state initially, and therefore a penetrating current flows between the power source VDD2 and GND through the PMOST 101, 103 and the NMOST 105. This state is in continuation as far as the PMOST 101 or the PMOST 103 is not turned OFF. Consequently, in order to avoid this penetrating current, 1) a method of turning the PMOST 101 OFF, and then 2) a method of turning the PMOST 103 OFF is considered.
1) A method of turning OFF the PMOST 101
In order to turn the PMOST 101 OFF, it is necessary to turn the PMOST 102 and 104 ON to receive a charge supplied from the power source VDD2 that is connected to the source of the PMOST 102 to thereby raise the gate electric potential of the PMOST 101 to 13 V or more. The electric potential of the inverted input signal (/IN) of the input signal (IN) is xe2x80x9cLoxe2x80x9d of 0 V, and hence the NMOST 106 is turned OFF and the PMOST 104 is turned ON. If the PMOST 102 is turned ON, then the NMOST 106 is turned OFF. Therefore, the gate electric potential of the PMOST 101 can be rapidly charged up to 15 V without the penetrating current flowing. In order to do this, nevertheless, the gate electric potential of the PMOST 102 must be lower than 13 V, that is, it is necessary to discharge a charge to the GND from the gate of the PMOST 102 through the NMOST 105. However, as mentioned before, the discharge from the gate of the PMOST 102 is not adequate due to the penetrating current flowing through the PMOST 101, 103 and the NMOST 105. As a result, by designing the PMOST 101, 103 and the NMOST 105 under the condition that the penetrating current is flowing so that the drain electric potential of the NMOST 105 is smaller than 13 V, then the PMOST 101 can be turned OFF.
2) A method of turning OFF the PMOST 103
To turn the PMOST 103 OFF, it is necessary to raise the voltage between the gate and the source thereof to xe2x88x922 V or more. Because the electric potential of the input signal (IN) is 5 V, similarly, the gate electric potential of the PMOST 103 is 5 V. Therefore, the source electric potential of the PMOST 103 must be reduced to 7 V or less. In this case also, by designing, under the condition that the penetrating current is flowing, the PMOST 101, 103 and the NMOST 105 so that the source electric potential of the PMOST 103 is less than 7 V, then the PMOST 103 can be turned OFF.
In any case, in the above 2 methods, the design of the PMOSTs 101, 103 and the NMOST 105 must be made with the ON resistance taken into consideration so that even if the penetrating current is flowing, level conversion can be conducted by cutting the flow of the penetrating current. Further, in order to operate speedily, the current that flows from the power source VDD2 that is connected to the source of the PMOST 101 to the gate of the PMOST 102 via the PMOST 101 and 103 must be suppressed. This has to do with whether or not to increase the current flowing out to the GND from the gate of the PMOST 102 via the NMOST 105. To swiftly raise the output (OUT) to xe2x80x9cHixe2x80x9d once the PMOST 102 is turned ON, the current drive ability of the PMOST 102 and 104 must also be taken into consideration.
Regarding the input signal (IN), when the electric potential thereof changes to xe2x80x9cLoxe2x80x9d of 0 V from xe2x80x9cHixe2x80x9d of 5 V, the roles of the PMOST 101 and 102, the PMOST 103 and 104, the NMOST 105 and 106 are merely exchanged, respectively. Therefore, it is also acceptable to replace the respective transistors in the above described operation.
Accordingly, regarding the exemplified conventional level shifter of FIG. 23, the PMOST 101 to 104 has the lowest current driving ability, and hence the point here is to design the NMOST 105 and 106 so that they have a higher current driving ability when compared with that of the PMOST 101 to 104. In accordance therewith, it is appropriate to design the channel width of the NMOST 105 and 106 longer as voltage amplitudes having a large difference become larger for level conversion. However, the level shifter itself becomes big, and an input gate capacitance is also increased, whereby a circuit of an upper current becomes large as well. Consequently, this invites an increase of the area occupied by the circuit.
The same thing can be observed in regards to the exemplified conventional level shifter of FIG. 24.
The present invention has been made in view of the above problem, and therefore has an object to provide a new level shifter that reduces the consumption power which originates from a penetrating current that occurs during a transient period of an operation, make a level conversion of voltage amplitudes having a large difference easy, and improve its operational speed as well whereby an increase of an area occupied by a circuit is repressed.
According to an aspect of the present invention, there is provided a level shifter comprising a first MOS transistor of a first conductive type having a source that is connected to a first power source and a gate to which a first input signal is inputted, and a second MOS transistor of a conductive type that is similar to the first conductive type having a source that is connected to the first power source and a gate to which a second input signal that is an inverted signal of the first input signal is inputted.
Further, the level shifter of the present invention has a third MOS transistor of a second conductive type, which is a conductive type that is different from the first conductive type, having a drain that is connected to a drain of the first MOS transistor and a gate to which the first input signal is inputted, and a fourth MOS transistor of a conductive type that is similar to the second conductive type having a drain that is connected to a drain of the second MOS transistor and a gate to which the second input signal is inputted.
Further, the level shifter of the present invention has a fifth MOS transistor of a conductive type that is similar to the second conductive type having a drain that is connected to a source of the third MOS transistor and a gate that is connected to a drain of the second MOS transistor, and a sixth MOS transistor of a conductive type that is similar to the second conductive type having a drain that is connected to a source of the fourth MOS transistor and a gate that is connected to a drain of the first MOS transistor.
Still further, the level shifter of the present invention has a first voltage regulating circuit that is connected between a source of the fifth MOS transistor and a second power source, and a second voltage regulating circuit that is connected between a source of the sixth MOS transistor and the second power source.
This level shifter converts the first and second input signals of a first voltage amplitude to a signal of a second voltage amplitude to thereby output a signal from at least one of a drain of the first MOS transistor or a drain of the second MOS transistor. In a transient period of a level conversion operation, the 2 voltage regulating circuits regulate a source electric potential of the fifth MOS transistor and a source electric potential of the sixth MOS transistor, making the level conversion of voltage amplitudes having a large difference easy and hence resolving the above problem.
According to another aspect of the present invention, there is provided a level shifter comprising a first MOS transistor of a first conductive type having a source that is connected to a first power source and a gate to which a first input signal is inputted, and a second MOS transistor of a conductive type that is similar to the first conductive type having a source that is connected to the first power source and a gate to which a second input signal that is an inverted signal of the first input signal is inputted.
Further, the level shifter has a third MOS transistor of a second conductive type, which is a conductive type that is different from the first conductive type, having a drain that is connected to the drain of the first MOS transistor and a gate that is connected the drain of the second MOS transistor, and a fourth MOS transistor of a conductive type that is similar to the second conductive type having a drain that is connected to the drain of the second MOS transistor and a gate that is connected to the drain of the first MOS transistor.
Still further, the level shifter has a first voltage regulating circuit that is connected between a source of the third transistor and a second power source, and a second voltage regulating circuit that is connected between a source of the fourth MOS transistor and the second power source.
This level shifter converts the first and second input signals of a first voltage amplitude to a signal of a second voltage amplitude to thereby output a signal from at least one of the drain of the first MOS transistor or the drain of the second MOS transistor. In the transient period of a level conversion operation, the 2 voltage regulating circuits regulate a source electric potential of the third MOS transistor and a source electric potential of the fourth MOS transistor, making the level conversion of voltage amplitudes having a large difference easy and hence resolving the above problem.
The above-mentioned voltage regulating circuits may have a MOS transistor that has a drain and a gate thereof connected.
In addition, the above-mentioned voltage regulating circuits may be circuits that have a resistor which contains a poly-silicon layer or a silicon layer doped with an impurity element.
Further, the above-mentioned voltage regulating circuits may be circuits that include a MOS transistor having a constant voltage applied to a gate thereof.